[RISCV] Update mir tests.
authorHsiangkai Wang <kai.wang@sifive.com>
Wed, 22 Sep 2021 23:47:50 +0000 (07:47 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Thu, 23 Sep 2021 01:42:16 +0000 (09:42 +0800)
commitebc5feb4ed6b1f59a000669030f9639bf1763403
tree2cf3ac58fbd5f3695e6874f33f0f35eefeac1a62
parent1ed69bb86eb188ab23f62c266d2d23846588e768
[RISCV] Update mir tests.
12 files changed:
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir