riscv: dma-mapping: only invalidate after DMA, not flush
authorArnd Bergmann <arnd@arndb.de>
Wed, 16 Aug 2023 23:23:34 +0000 (00:23 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 1 Sep 2023 16:07:44 +0000 (09:07 -0700)
commiteb746180132a555da8cfb02d98cb6d0a9d58e870
tree7a13de90b7e8c4403b3ca2ca9b92112b5de03246
parent06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5
riscv: dma-mapping: only invalidate after DMA, not flush

No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU,  there is a driver bug that is likely
made worse by overwriting that buffer.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20230816232336.164413-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/mm/dma-noncoherent.c