aarch64: Fix DWARF frame register sizes for predicates
authorRichard Sandiford <richard.sandiford@arm.com>
Fri, 13 Jan 2023 10:01:32 +0000 (10:01 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Fri, 13 Jan 2023 10:01:32 +0000 (10:01 +0000)
commiteb4994545fbd2a670e422f6e98c16e4ed60ac53e
tree817f3df6de411ac2834a11087abe44862e34e10a
parent3893c9c0a16832f55d8d0827f50c48a56c52f6e7
aarch64: Fix DWARF frame register sizes for predicates

Jakub pointed out that __builtin_init_dwarf_reg_size_table
set the size of predicate registers to their current runtime
size when compiled with +sve, but to 8 bytes otherwise.
As explained in the comment, both behaviours are wrong.
Predicates change size with VL and should never need to be
restored during unwinding.

In contrast, the call-saved FP&SIMD frame registers are 8 bytes
(even though the hardware registers are at least 16 bytes) and
the call-clobbered registers have zero size.  A zero size seems
correct for predicates too.

gcc/
* config/aarch64/aarch64.cc (aarch64_dwarf_frame_reg_mode): New
function.
(TARGET_DWARF_FRAME_REG_MODE): Define.

gcc/testsuite/
* gcc.target/aarch64/dwarf_reg_size_1.c: New test.
* gcc.target/aarch64/dwarf_reg_size_2.c: Likewise.
gcc/config/aarch64/aarch64.cc
gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c [new file with mode: 0644]