clk: mediatek: Add MT8188 vppsys0 clock support
authorGarmin.Chang <Garmin.Chang@mediatek.com>
Fri, 31 Mar 2023 12:36:17 +0000 (20:36 +0800)
committerStephen Boyd <sboyd@kernel.org>
Fri, 31 Mar 2023 18:51:22 +0000 (11:51 -0700)
commiteb48cccda09597a309d66331744e1b8edf196a67
tree1ff4b63c9ef309fcc69f1c62423a8429541dbba8
parentbb87c1109ce2f4c947b5b92a1f82ec75f8f969f8
clk: mediatek: Add MT8188 vppsys0 clock support

Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/Kconfig
drivers/clk/mediatek/Makefile
drivers/clk/mediatek/clk-mt8188-vpp0.c [new file with mode: 0644]