[CodeGen] Introduce a generic MEMBARRIER instruction [mostly-nfc]
authorPhilip Reames <preames@rivosinc.com>
Wed, 11 Jan 2023 15:18:11 +0000 (07:18 -0800)
committerPhilip Reames <listmail@philipreames.com>
Wed, 11 Jan 2023 15:26:27 +0000 (07:26 -0800)
commiteb44226986fcbeb4325e5f668e5646e9646958bc
treefef2a03ad7887edc2f6543081a03f0a085b2b648
parenta3fa6b86fa424dab1f1b6cbc38e27c8c3364f2f4
[CodeGen] Introduce a generic MEMBARRIER instruction [mostly-nfc]

This is a follow up to D141317 which extends the common code to include a target independent pseudo instruction. This is an alternative to (subset of) D92842 which tries to be as close to NFC as possible.

A couple things to call out.
* The test change in X86 is because we loose the scheduling information on the instruction. However, I think this was actually a bug in x86 since no instruction was emitted for a MEMBARRIER. Concluding that a meta instruction has latency just seems wrong?
* I intentionally left some parts of D92842 out. Specifically, several of the changes in the X86 code (data independence and outlining) appear functional, and likely worthy of their own review. Additionally, I'm not handling ARM/AArch64 at all. Those targets need the ordering whereas none of the others do. I want to get this in and tested before retrofitting in ordering to support those targets.

Differential Revision: https://reviews.llvm.org/D141408
16 files changed:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/Target.td
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
llvm/lib/Target/VE/VEInstrInfo.td
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/XCore/XCoreInstrInfo.td
llvm/test/CodeGen/X86/atomic-idempotent.ll
llvm/unittests/MIR/MachineMetadata.cpp