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[RISCV] Revise check names for unaligned memory op tests [nfc]
authorPhilip Reames <preames@rivosinc.com>
Thu, 20 Jul 2023 20:34:22 +0000 (13:34 -0700)
committerPhilip Reames <listmail@philipreames.com>
Thu, 20 Jul 2023 20:36:53 +0000 (13:36 -0700)
commiteb3f2fe467f10b29c407e642e8a505ee6800c1d8
tree0cb715da99fc5fe9d87ad2ba4ff572b0506506b2tree | snapshot
parent760c208f6ff9e97a9a11523c00874a1eec4f876bcommit | diff
[RISCV] Revise check names for unaligned memory op tests [nfc]

This has come up a few times in review; the current ones seem to be universally confusing.  Even I as the original author of most of these get confused.  Switch to using the SLOW/FAST naming used by x86, hopefully that's a bit clearer.
llvm/test/CodeGen/RISCV/memcpy-inline.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll diff | blob | history
llvm/test/CodeGen/RISCV/unaligned-load-store.ll diff | blob | history
Domain: System / Toolchain;