dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 2 Apr 2022 07:30:34 +0000 (08:30 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 13 Apr 2022 10:21:04 +0000 (12:21 +0200)
commiteb2789785428e2dbc3d5f413b16c67ff90d828c1
tree61e662b72c77d34707342e56d3038a3128104c98
parent3123109284176b1532874591f7c81f3837bbdc17
dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions

Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r9a07g043-cpg.h [new file with mode: 0644]