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author	Egor Chesakov <Egor.Chesakov@microsoft.com>
	Thu, 2 Jul 2020 17:14:07 +0000 (10:14 -0700)
committer	GitHub <noreply@github.com>
	Thu, 2 Jul 2020 17:14:07 +0000 (10:14 -0700)
commit	eaf3c78b79ad83c205ca16d372255fcfd226fcae
tree	2e456653876909660bed5f2532122c80efd8025c	tree \| snapshot
parent	a92f4f02dcbbd76cb9edf682424d001b9eb6d870	commit \| diff

[Arm64] ASIMD InsertScalar and rename to ShiftLeftAndInsert ShiftRightAndInsert (#38680)

* Implements InsertScalar

* Uses InsertScalar to implement Vector128<T>.WithLower() and Vector128<T>.WithUpper()

* Renames ShiftLeftLogicalAndInsert to ShiftLeftAndInsert and ShiftRightLogicalAndInsert to ShiftRightAndInsert

47 files changed:

src/coreclr/src/jit/hwintrinsic.cpp		diff \| blob \| history
src/coreclr/src/jit/hwintrinsicarm64.cpp		diff \| blob \| history
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp		diff \| blob \| history
src/coreclr/src/jit/hwintrinsiclistarm64.h		diff \| blob \| history
src/coreclr/src/jit/lowerarmarch.cpp		diff \| blob \| history
src/coreclr/src/jit/lsraarm64.cpp		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_r.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_ro.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_r.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_ro.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part4_r.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part4_ro.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part5_r.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part5_ro.csproj		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/InsertScalar.Vector128.Double.1.cs	[new file with mode: 0644]	blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/InsertScalar.Vector128.Int64.1.cs	[new file with mode: 0644]	blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/InsertScalar.Vector128.UInt64.1.cs	[new file with mode: 0644]	blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part2.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part3.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part4.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part5.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.Byte.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.Byte.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.Int16.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.Int16.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.Int32.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.Int32.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.Int64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.Int64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.SByte.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.SByte.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.UInt16.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.UInt16.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.UInt32.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.UInt32.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector128.UInt64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector128.UInt64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.Byte.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.Byte.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.Int16.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.Int16.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.Int32.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.Int32.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.SByte.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.SByte.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.UInt16.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.UInt16.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsert.Vector64.UInt32.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsert.Vector64.UInt32.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsertScalar.Vector64.Int64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsertScalar.Vector64.Int64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftAndInsertScalar.Vector64.UInt64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftLeftLogicalAndInsertScalar.Vector64.UInt64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftRightAndInsertScalar.Vector64.Int64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftRightLogicalAndInsertScalar.Vector64.Int64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftRightAndInsertScalar.Vector64.UInt64.cs	[moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/ShiftRightLogicalAndInsertScalar.Vector64.UInt64.cs with 90% similarity]	diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/InsertScalarTest.template	[new file with mode: 0644]	blob
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/AdvSimd.PlatformNotSupported.cs		diff \| blob \| history
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/AdvSimd.cs		diff \| blob \| history
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Vector128.cs		diff \| blob \| history
src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs		diff \| blob \| history

Domain: Dotnet / Core;

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