arm: dra7xx: clock: Add the dplls data
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 12 Feb 2013 21:29:05 +0000 (21:29 +0000)
committerTom Rini <trini@ti.com>
Mon, 11 Mar 2013 15:06:11 +0000 (11:06 -0400)
commitea8eff1fe080bef7c5cdfea734d8ac4cdd957c4c
treecd8c94874ac1a497b86528f009434e7dd80a206f
parentd4e4129c31cf571824a1b34aa0b9210c876be718
arm: dra7xx: clock: Add the dplls data

A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap4/hw_data.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/include/asm/omap_common.h