drm/i915/mtl: Add vswing programming for C10 phys
authorMika Kahola <mika.kahola@intel.com>
Thu, 13 Apr 2023 21:24:38 +0000 (14:24 -0700)
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Fri, 14 Apr 2023 15:12:40 +0000 (08:12 -0700)
commitea8af87ae6be578b3b633ad6aa9188b0ce4cd7ee
tree745085eba0962bed55f6a2ce020ec30b5a8d5ea5
parent51390cc0e00a378b7c152bb6f63efc0a01b59d20
drm/i915/mtl: Add vswing programming for C10 phys

C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.

Bspec: 65449

v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
    and preemphasis 1 instead of two times of level 1 preemphasis 0.
    Fix this in the driver code as well.
v3: VSwing update (Clint)
v4: Add vboost termination ctl programming(Imre)
    Fix tx llogic and other nits
    Restrict C10 vdr ctl register access for C10 phy(RK)
v5: Program vboots, termination ctl for both lanes(Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>(v3)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-5-radhakrishna.sripada@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c
drivers/gpu/drm/i915/display/intel_cx0_phy.h
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c