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drm/bridge: tc358767: increase CLRSIPO count
authorLucas Stach <l.stach@pengutronix.de>
Wed, 6 Jul 2022 13:28:11 +0000 (15:28 +0200)
committerMarek Vasut <marex@denx.de>
Wed, 10 Aug 2022 23:45:32 +0000 (01:45 +0200)
commitea6490b02240bd7939a3a13bc8d3f25046c01585
tree097c4c173edc7f36c446149cb7d74b0243a3d9cctree | snapshot
parent5fa9e16191204b6ead0c31e8f3b6ef92ddd8183ecommit | diff
drm/bridge: tc358767: increase CLRSIPO count

The current CLRSIPO count is marginal and does not work with high
DSI clock rates. Increase it a bit to allow the DSI link to work at
up to 1Gbps lane speed.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220706132812.2171250-2-l.stach@pengutronix.de
drivers/gpu/drm/bridge/tc358767.c diff | blob | history
Domain: System / Kernel;