[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.

[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.

Instead of zero extending the inputs by masking. We can shift them
left instead. This is cheaper when we don't zext.w instruction.

This does make the case where the inputs are already zero extended
or freely zero extendable worse though.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155530