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(parent: 14d9934) | patch
[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
authorMichael Maitland <michaeltmaitland@gmail.com>
Thu, 3 Nov 2022 17:27:32 +0000 (10:27 -0700)
committerMichael Maitland <michaeltmaitland@gmail.com>
Wed, 30 Nov 2022 19:09:21 +0000 (11:09 -0800)
commite9f2bac9a07d4104d49b63408014d4e036c614ac
tree871c107ce212fd25cd42429bf44b9be2a5683c2btree | snapshot
parent14d993435b147dd1cc4a30afda32ebbff9fb0b3dcommit | diff
[RISCV][Codegen] Account for LMUL in Vector floating-point instructions

It is likley that subtargets act differently for vector floating-point instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

Differential Revision: https://reviews.llvm.org/D137426
llvm/lib/Target/RISCV/RISCVInstrInfoV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/lib/Target/RISCV/RISCVScheduleV.td diff | blob | history
Domain: System / Toolchain;