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(parent: 40a632a) | patch
[VE] Support Transfer Control Instructions in MC layer
authorKazushi (Jam) Marukawa <marukawa@nec.com>
Tue, 9 Jun 2020 08:39:03 +0000 (10:39 +0200)
committerSimon Moll <simon.moll@emea.nec.com>
Tue, 9 Jun 2020 08:41:42 +0000 (10:41 +0200)
commite9eafb7be9da270d82cb0e784306a30074ab447d
tree56ac1d89a4ed58a08ea691e8efe6720f5849c1actree | snapshot
parent40a632a335119fe3e8d5d500a5d2641998314ecbcommit | diff
[VE] Support Transfer Control Instructions in MC layer

Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions.  Add FENCEI/FENCEM/FENCEC/SVOB instructions
also.  Add new instruction format to represent FENCE* instructions too.

Differential Revision: https://reviews.llvm.org/D81440
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp diff | blob | history
llvm/lib/Target/VE/VEInstrFormats.td diff | blob | history
llvm/lib/Target/VE/VEInstrInfo.td diff | blob | history
llvm/test/MC/VE/FENCE.s [new file with mode: 0644] blob
llvm/test/MC/VE/SVOB.s [new file with mode: 0644] blob
Domain: System / Toolchain;