mfd: db8500-prcmu: Update stored DSI PLL divider value
authorUlf Hansson <ulf.hansson@linaro.org>
Tue, 14 May 2013 13:14:55 +0000 (15:14 +0200)
committerSamuel Ortiz <sameo@linux.intel.com>
Thu, 16 May 2013 22:42:34 +0000 (00:42 +0200)
commite9d7b4b5691cac4dce6c5eed9e217e50e24edef7
tree02a1dbba87708c64445379937b7497487dfb8fe0
parent0b8ebdb18888c55588b932f4f564b9c9529de627
mfd: db8500-prcmu: Update stored DSI PLL divider value

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
drivers/mfd/db8500-prcmu.c