pinctrl: renesas: r8a77995: Add bias pinconf support
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 30 Jun 2021 14:50:43 +0000 (16:50 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 13 Jul 2021 07:43:34 +0000 (09:43 +0200)
commite9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c
treedd9bc23170b2d3ce6fb4be8195cf99b6d19548b0
parent7ebaa41047738d46fca6376b3f1765ef69c463c5
pinctrl: renesas: r8a77995: Add bias pinconf support

Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and
pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using
some parts from the common R-Car bias handling, which requires making
rcar_pin_to_bias_reg() public.

R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE#
(GP_3_1) pins.  Unlike all other pins, they are controlled by different
bits in the LSI pin pull-up/down control register (PUD2) than in the LSI
pin pull-enable register (PUEN2).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
drivers/pinctrl/renesas/pfc-r8a77995.c
drivers/pinctrl/renesas/pinctrl.c
drivers/pinctrl/renesas/sh_pfc.h