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author	Fraser Cormack <fraser@codeplay.com>
	Tue, 1 Feb 2022 10:54:39 +0000 (10:54 +0000)
committer	Fraser Cormack <fraser@codeplay.com>
	Tue, 1 Feb 2022 11:06:56 +0000 (11:06 +0000)
commit	e9ceeedf30aa362a50c644a58c03596cff3907fe
tree	475de056baee31310377a2f14b010903d03211cc	tree \| snapshot
parent	8d1169cf74ecd362cb7992fafe7eeca9771a625f	commit \| diff

[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests

65 files changed:

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/combine-sats.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/constant-folding.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll		diff \| blob \| history

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