[DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 17 Jul 2023 14:34:52 +0000 (15:34 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 17 Jul 2023 14:50:09 +0000 (15:50 +0100)
commite9caa37e9c69f6a6e5ab59d33b9d492054819ded
tree8d7565d3d2e3b6645b3410be68ad7ac7c50affde
parentfbfff1caff18eee5841c3946e58fa2d7964a1286
[DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits

Inspired by some of the cases from D145468

Let SimplifyDemandedBits handle the narrowing of lshr to half-width if we don't require the upper bits, the narrowed shift is profitable and the zext/trunc are free.

A future patch will propose the equivalent shl narrowing combine.

Differential Revision: https://reviews.llvm.org/D146121
23 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AMDGPU/idot4s.ll
llvm/test/CodeGen/AMDGPU/idot4u.ll
llvm/test/CodeGen/AMDGPU/idot8s.ll
llvm/test/CodeGen/AMDGPU/idot8u.ll
llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
llvm/test/CodeGen/AMDGPU/shift-i128.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
llvm/test/CodeGen/X86/3addr-or.ll
llvm/test/CodeGen/X86/and-shift.ll
llvm/test/CodeGen/X86/bswap.ll
llvm/test/CodeGen/X86/combine-bitreverse.ll
llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
llvm/test/CodeGen/X86/extract-bits.ll
llvm/test/CodeGen/X86/h-registers-0.ll
llvm/test/CodeGen/X86/lzcnt-cmp.ll
llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
llvm/test/CodeGen/X86/zext-lshr.ll