intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP
authorRafael Antognolli <rafael.antognolli@intel.com>
Tue, 9 Oct 2018 21:14:15 +0000 (14:14 -0700)
committerMarge Bot <emma+marge@anholt.net>
Mon, 20 Dec 2021 17:58:13 +0000 (17:58 +0000)
commite9b509755b4e1621274ff80117ad9858795579d4
tree3d0764a33d4554ef060b9ae9914ad1f7ca8151b2
parente6fc231184fe9ed73dde0d79aae8534656f45962
intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP

On XeHP+, Binding Table Pointers are an offset relative to the Surface
State Base Address anymore. Instead, they are relative to the State
Binding Table Pool Address, which is set by the command above.

We emit that command (pointing to the same address as the Surface
State Base Addresss), and everything should stay working as before.

Reworks:
 * Jordan: Add iris
 * Jordan: Drop i965
 * Ken: Set MOCS to avoid a major perf impact. (Found by Felix DeGrood.)
 * Jordan: Shrink size from 2MiB to actual iris, anv usage
 * Lionel: Add BINDING_TABLE_POOL_BLOCK_SIZE

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4995
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
[jordan.l.justen@intel.com: Add Iris, adjust sizes]

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
src/gallium/drivers/iris/iris_state.c
src/intel/vulkan/genX_cmd_buffer.c