perf: Fix LLC-* events on Intel Nehalem/Westmere
authorAndi Kleen <ak@linux.intel.com>
Thu, 3 Mar 2011 02:34:48 +0000 (10:34 +0800)
committerIngo Molnar <mingo@elte.hu>
Fri, 4 Mar 2011 10:32:53 +0000 (11:32 +0100)
commite994d7d23a0bae34cd28834e85522ed4e782faf7
treef9b08a69bdccf047cba9449adee4dd86ed1e8892
parenta7e3ed1e470116c9d12c2f778431a481a6be8ab6
perf: Fix LLC-* events on Intel Nehalem/Westmere

On Intel Nehalem and Westmere CPUs the generic perf LLC-* events count the
L2 caches, not the real L3 LLC - this was inconsistent with behavior on
other CPUs.

Fixing this requires the use of the special OFFCORE_RESPONSE
events which need a separate mask register.

This has been implemented by the previous patch, now use this infrastructure
to set correct events for the LLC-* on Nehalem and Westmere.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1299119690-13991-3-git-send-email-ming.m.lin@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_intel.c