clk: qoriq: modify MAX_PLL_DIV to 32
authorZhao Qiang <qiang.zhao@nxp.com>
Wed, 16 Sep 2020 03:03:10 +0000 (11:03 +0800)
committerStephen Boyd <sboyd@kernel.org>
Wed, 14 Oct 2020 02:48:09 +0000 (19:48 -0700)
commite9501b975a9efb499f2ecbe3374d433b25c5b4f4
treecb0aab171fea024a8154e36cca142caa91bb6721
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5
clk: qoriq: modify MAX_PLL_DIV to 32

On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-qoriq.c