clk: sunxi: Add Allwinner H3/H5 CLK driver
authorJagan Teki <jagan@amarulasolutions.com>
Thu, 2 Aug 2018 10:13:02 +0000 (15:43 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Fri, 18 Jan 2019 16:49:08 +0000 (22:19 +0530)
commite945816efbd3541f4a4e877e13221768f0b9f775
tree316d499293b728011e66f78a5fdf5473132497a0
parent99ba4308701c51dcf425dbef42c6f87fcc9c42a2
clk: sunxi: Add Allwinner H3/H5 CLK driver

Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi/Kconfig
drivers/clk/sunxi/Makefile
drivers/clk/sunxi/clk_h3.c [new file with mode: 0644]