[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 12 Mar 2020 20:16:40 +0000 (20:16 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 12 Mar 2020 20:16:57 +0000 (20:16 +0000)
commite91feeed21ee16abdb73f6e8cd471a253136e2cf
treee123069ca06231521cbbc8648d00eaf2d3a0c855
parent9975dc38bf734b4d86eab61269080ca231379d23
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support

This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions.

This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.

Differential Revision: https://reviews.llvm.org/D76070
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/lib/Target/AMDGPU/EvergreenInstructions.td
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
llvm/test/CodeGen/AMDGPU/fshl.ll
llvm/test/CodeGen/AMDGPU/fshr.ll
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
llvm/test/CodeGen/AMDGPU/permute.ll
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
llvm/test/CodeGen/AMDGPU/shift-i128.ll