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(parent: 373b900) | patch
riscv: cpu: Add nx25 to support RISC-V
authorRick Chen <rick@andestech.com>
Tue, 26 Dec 2017 05:55:48 +0000 (13:55 +0800)
committerTom Rini <trini@konsulko.com>
Fri, 12 Jan 2018 13:05:12 +0000 (08:05 -0500)
commite8e39597a33cc53aacbaf4ef5cae60ed86d6a20a
treec31439c473ea9fce54ff32851bf2d3058acab33atree | snapshot
parent373b9003410b44a1133060c2e63483b278fb476bcommit | diff
riscv: cpu: Add nx25 to support RISC-V

Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
arch/riscv/cpu/nx25/Makefile [new file with mode: 0644] blob
arch/riscv/cpu/nx25/cpu.c [new file with mode: 0644] blob
arch/riscv/cpu/nx25/start.S [new file with mode: 0644] blob
arch/riscv/cpu/nx25/u-boot.lds [new file with mode: 0644] blob
Domain: System / Kernel;