clk: renesas: r8a7742: Add clk entry for VSPR
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 31 Aug 2020 18:03:12 +0000 (19:03 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 4 Sep 2020 07:42:01 +0000 (09:42 +0200)
commite8d8e9a3d0b28c99a0f0f7fc168fd6eff345fcc3
tree766eb46eea36ffb5b21e66dccc9b86f527b89998
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5
clk: renesas: r8a7742: Add clk entry for VSPR

Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module
can be used on R8A7742 (RZ/G1H) SoC.

Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that
VSP1 clock names are in sync.

Note: The entry for VSPR clock was accidentally dropped from RZ/G manual
when all the information related to RT were removed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7742-cpg-mssr.c