[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))
authorCraig Topper <craig.topper@sifive.com>
Sun, 23 Oct 2022 04:35:38 +0000 (21:35 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sun, 23 Oct 2022 04:51:45 +0000 (21:51 -0700)
commite8b3ffa532b8ebac5dcdf17bb91b47817382c14d
treebff7de78962b330aceb93059a27320e626d3b6eb
parentc9447c62966e5ec60ec277e4a7d75420224f53f6
[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))

(sra X, BW-1) is either 0 or -1. So the multiply is a conditional
negate of Y.

This pattern shows up when type legalizing wide multiplies involving
a sign extended value.

Fixes PR57549.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D133399
13 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/AMDGPU/mad_64_32.ll
llvm/test/CodeGen/PowerPC/pr45448.ll
llvm/test/CodeGen/RISCV/mul.ll
llvm/test/CodeGen/RISCV/xaluo.ll
llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
llvm/test/CodeGen/X86/extmul128.ll
llvm/test/CodeGen/X86/muloti.ll
llvm/test/CodeGen/X86/smul_fix_sat.ll
llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
llvm/test/CodeGen/X86/vec_smulo.ll
llvm/test/CodeGen/X86/xmulo.ll