clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 30 Aug 2019 13:45:10 +0000 (15:45 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 1 Oct 2019 08:24:49 +0000 (10:24 +0200)
commite8adb3a0f74cf568030b7bd1f77d877e6f308d17
tree4ae9e94ec62c3eefc10263f1953f1156760782c2
parentb5dea62d34042d173ba1d1887c8dd40262423d68
clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()

The .set_rate() callback for the SD clocks is always called with a valid
clock rate, returned by .round_rate().  Hence there is no need to
iterate through the divider table twice: once to repeat the work done by
.round_rate(), and a second time to find the corresponding divider
entry.

Just iterate once, looking for the divider that matches the passed clock
rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be
drivers/clk/renesas/rcar-gen3-cpg.c