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(parent: 45f1287) | patch
RISC-V: Add RVV constraints.
authorzhongjuzhe <juzhe.zhong@rivai.ai>
Tue, 30 Aug 2022 06:13:51 +0000 (14:13 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Thu, 1 Sep 2022 01:55:21 +0000 (09:55 +0800)
commite8089aff3602447cd66ea723802d43cec4e7ec02
tree9fecf28370e83a361ce3175a6a62fe28005ca061tree | snapshot
parent45f1287268200ffd551faca83d5e819b279ade9fcommit | diff
RISC-V: Add RVV constraints.

gcc/ChangeLog:

* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
"vr" constraint.
(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
(vp): Add poly constraint.
gcc/config/riscv/constraints.md diff | blob | history
Domain: System / Toolchain;