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[ARM] Assign cost of scaling for Cortex-R52
authorJaved Absar <javed.absar@arm.com>
Tue, 18 Oct 2016 09:08:54 +0000 (09:08 +0000)
committerJaved Absar <javed.absar@arm.com>
Tue, 18 Oct 2016 09:08:54 +0000 (09:08 +0000)
commite7c338081a8e5f145654781a58175f5edb3aa9d6
tree208ac227cae0719f00a23890a8d642ac0441db24tree | snapshot
parent4ddc92b6cdcb1a15b8973fad366cd70a06446439commit | diff
[ARM] Assign cost of scaling for Cortex-R52

This patch assigns cost of the scaling used in addressing for Cortex-R52.

On Cortex-R52 a negated register offset takes longer than a non-negated
register offset, in a register-offset addressing mode.

Differential Revision: http://reviews.llvm.org/D25670

Reviewer: jmolloy
llvm-svn: 284460
llvm/lib/Target/ARM/ARM.td diff | blob | history
llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll diff | blob | history
Domain: System / Toolchain;