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riscv: dts: microchip: fix the mpfs' mailbox regs
authorConor Dooley <conor.dooley@microchip.com>
Tue, 7 Mar 2023 21:10:54 +0000 (21:10 +0000)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 15 Mar 2023 14:43:48 +0000 (14:43 +0000)
commite77da13b8e3626fc6d01287fba7c1eee4ebfe018
tree19b73a7bc0867e87629ccb3d90b7be7383b62cf3tree | snapshot
parent0e9b70c1e3623fa110fb6be553e644524228ef60commit | diff
riscv: dts: microchip: fix the mpfs' mailbox regs

The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI cannot be accessed as it sits inside the current first range. The
driver & binding have been adapted to account for both two & three
ranges, so fix the dts too.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/microchip/mpfs.dtsi diff | blob | history
Domain: System / Kernel;