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(parent: 8d6310a) | patch
dts: stm32mp1: clock tree update
authorPatrick Delaunay <patrick.delaunay@st.com>
Wed, 30 Jan 2019 12:07:05 +0000 (13:07 +0100)
committerTom Rini <trini@konsulko.com>
Sat, 9 Feb 2019 12:50:57 +0000 (07:50 -0500)
commite74b74c52876d776dda7a7ee5e2a8d555eaa5c4f
tree960fda40cbbcddb03270d37572a4bfa42b13e71dtree | snapshot
parent8d6310aa0ba2bee92e14c0702c5ceec64943383acommit | diff
dts: stm32mp1: clock tree update

- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi diff | blob | history
include/dt-bindings/clock/stm32mp1-clks.h diff | blob | history
Domain: System / Kernel;