[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand...
authorCraig Topper <craig.topper@sifive.com>
Thu, 16 Jun 2022 21:45:44 +0000 (14:45 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 16 Jun 2022 21:55:14 +0000 (14:55 -0700)
commite6c7a3a54ffaf0001017f619faf2fa260fb517b4
treef1cba8db186c9191593f41312c73127c31780b75
parent011e0604ebc9d85db3585ebb2f63df465f726417
[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources.

MinRCSize is 4 and prevents constrainRegClass from changing the
register class if the new class has size less than 4.

IMPLICIT_DEF gets a unique vreg for each use and will be removed
by the ProcessImplicitDef pass before register allocation. I don't
think there is any reason to prevent constraining the virtual register
to whatever register class the use needs.

The attached test case was previously creating a copy of IMPLICIT_DEF
because vrm8nov0 has 3 registers in it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D128005
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll [new file with mode: 0644]