ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 7 Sep 2012 05:39:15 +0000 (11:09 +0530)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tue, 25 Sep 2012 10:20:26 +0000 (11:20 +0100)
commite6b866e954a7f0d0144a951c158f3922dac1e6b9
tree9d0cbf02117228da9bda0071f2f949109a16f65b
parentdbee0c6fb4c1269b2dfc8b0b7a29907ea7fed560
ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/kernel/smp.c