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(parent: 2614319) | patch
intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11
authorDongwon Kim <dongwon.kim@intel.com>
Thu, 27 Jun 2019 16:54:33 +0000 (09:54 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Mon, 8 Jul 2019 17:54:37 +0000 (10:54 -0700)
commite6ac6d3224f0d69e537daef93b42a1762b7af760
tree5107c8fdec47c1bf51391b561590f43fde7af7c9tree | snapshot
parent2614319259e5c865606fb4f917c439e76196631fcommit | diff
intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11

correct bit fields information of CACHE_MODE_0 reg in current gen11.xml

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
src/intel/genxml/gen11.xml diff | blob | history
Domain: Graphics System / GL;