[amdgpu] Handle the case where there is no scavenged register.
authorMichael Liao <michael.hliao@gmail.com>
Fri, 16 Jul 2021 16:14:49 +0000 (12:14 -0400)
committerMichael Liao <michael.hliao@gmail.com>
Wed, 27 Oct 2021 22:37:27 +0000 (18:37 -0400)
commite6a4ba3aa603e542e6e0f7f7d9aca3cfa7c3f03f
tree33a48b0f1203222fe79308de2a057140f5cdc73e
parent32d45862fc03f4ccfe910ff3e59eff3d9dc3a42c
[amdgpu] Handle the case where there is no scavenged register.

- When an unconditional branch is expanded into an indirect branch, if
  there is no scavenged register, an SGPR pair needs spilling to enable
  the destination PC calculation. In addition, before jumping into the
  destination, that clobbered SGPR pair need restoring.
- As SGPR cannot be spilled to or restored from memory directly, the
  spilling/restoring of that SGPR pair reuses the regular SGPR spilling
  support but without spilling it into memory. As that spilling and
  restoring points are fully controlled, we only need to spill that SGPR
  into the temporary VGPR, which needs spilling into its emergency slot.
- The target-specific hook is revised to take additional restore block,
  where the restoring code is filled. After that, the relaxation will
  place that restore block directly before the destination block and
  insert an unconditional branch in any fall-through block into the
  destination block.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D106449
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/BranchRelaxation.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/AVR/AVRInstrInfo.cpp
llvm/lib/Target/AVR/AVRInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll