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(parent: 710f273) | patch
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE
authorLen Brown <len.brown@intel.com>
Thu, 12 Jan 2017 04:17:24 +0000 (23:17 -0500)
committerLen Brown <len.brown@intel.com>
Wed, 1 Mar 2017 05:14:03 +0000 (00:14 -0500)
commite651262477c6d8cba79dffc1a6039da43d9c96b0
tree75628064980e6094ef835f540196b01d64558d66tree | snapshot
parent710f273ba96182fd93ee8540ae06583c7d889d7ccommit | diff
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE

Decode MISC_ENABLE.NO_TURBO,
also use the #defines in msr-index.h for decoding this register

cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)

Although it is not architectural, decode also
MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).
documented to be present on: Core, P4, Intel-Xeon
reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.

Signed-off-by: Len Brown <len.brown@intel.com>
tools/power/x86/turbostat/turbostat.c diff | blob | history
Domain: System / Kernel;