clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
authorSamuel Holland <samuel@sholland.org>
Sun, 29 Dec 2019 02:59:20 +0000 (20:59 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 5 Feb 2020 21:22:43 +0000 (21:22 +0000)
commite619af70d133e0a1a30520f460b7433a708ebe2e
tree2124874819df004d1089faae6677eb9397774a3b
parent95c892061e903e612a2e2fe3ba29c3d0ad273df5
clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock

[ Upstream commit 47d64fef1f3ffbdf960d3330b9865fc9f12fdf84 ]

According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun8i-r.c