Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled

Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled

The default expansion for bswap16 is two extractions (shift/and)
followed by an insertation (ior) and then a zero extend. This can be improved
with ZBB enabled to just full byteswap followed by a (logical) shift right.
This patch adds a new pattern for this which does that.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu.

gcc/ChangeLog:

	PR target/106601
	* config/riscv/bitmanip.md (bswaphi2): New pattern.

gcc/testsuite/ChangeLog:

	PR target/106601
	* gcc.target/riscv/zbb_32_bswap-2.c: New test.
	* gcc.target/riscv/zbb_bswap-2.c: New test.