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(parent: 372e793) | patch
[mlir][sparse] support affine expression on sparse dimensions (codegen implementation)
authorPeiming Liu <peiming@google.com>
Thu, 17 Nov 2022 01:23:57 +0000 (01:23 +0000)
committerPeiming Liu <peiming@google.com>
Wed, 23 Nov 2022 00:04:55 +0000 (00:04 +0000)
commite5e4deca5ee8f0dcaeee58803ac397ae9d5a0a97
tree857f2ef2ece93944f1c2af694c43cf6090569a99tree | snapshot
parent372e7939d738d69e20db28c4433d4e161ed72397commit | diff
[mlir][sparse] support affine expression on sparse dimensions (codegen implementation)

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D138172
mlir/lib/Dialect/SparseTensor/Transforms/CodegenUtils.cpp diff | blob | history
mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp diff | blob | history
mlir/test/Dialect/SparseTensor/sparse_affine.mlir diff | blob | history
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir [new file with mode: 0644] blob
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir [new file with mode: 0644] blob
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir [new file with mode: 0644] blob
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir [new file with mode: 0644] blob
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir [new file with mode: 0644] blob
Domain: System / Toolchain;