review.tizen.org Git - platform/upstream/llvm.git/commit

projects / platform / upstream / llvm.git / commit

summary | shortlog | log | commit | commitdiff | tree
(parent: 47228f7) | patch

author	Hsiangkai Wang <kai.wang@sifive.com>
	Fri, 15 Jan 2021 11:29:51 +0000 (19:29 +0800)
committer	Hsiangkai Wang <kai.wang@sifive.com>
	Thu, 21 Jan 2021 03:51:35 +0000 (11:51 +0800)
commit	e5e329023bb119631e7a756b47598cb0ce9cea5f
tree	7d3a5dd9f4758dfff8ba7edf4b961c0631645eca	tree \| snapshot
parent	47228f785460cdd8f642c42876d394198d6b90c3	commit \| diff

[RISCV] Implement vlsseg intrinsics.

Define vlsseg intrinsics and pseudo instructions. Lower vlsseg intrinsics
to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94763

llvm/include/llvm/IR/IntrinsicsRISCV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll	[new file with mode: 0644]	blob

Domain: System / Toolchain;