author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Tue, 16 Jul 2019 20:25:43 +0000 (20:25 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Tue, 16 Jul 2019 20:25:43 +0000 (20:25 +0000) | ||
commit | e5b28b98e997f9b19ace6bcb95f6298b15b82cd4 | |
tree | 5252332f95cad854f66d0905ba09dd56e68c46a3 | tree | snapshot |
parent | 65e34a3143c48aff8a4200964abc195461f473ac | commit | diff |
llvm/lib/Target/AMDGPU/SOPInstructions.td | diff | blob | history | |
llvm/lib/Target/AMDGPU/VOP2Instructions.td | diff | blob | history | |
llvm/lib/Target/AMDGPU/VOP3Instructions.td | diff | blob | history | |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir | [new file with mode: 0644] | blob |