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(parent: 751035b) | patch
PCI/ATS: Cache PRI PRG Response PASID Required bit
authorBjorn Helgaas <bhelgaas@google.com>
Wed, 9 Oct 2019 21:07:51 +0000 (16:07 -0500)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 15 Oct 2019 21:39:10 +0000 (16:39 -0500)
commite5adf79a1d8086aefa56f48eeb08f8fe4e054a3d
treef053b77ce7824bd10bd5f99127159eb81663b5b8tree | snapshot
parent751035b8dc061ae434c3311bac9cd6d0e5e00f94commit | diff
PCI/ATS: Cache PRI PRG Response PASID Required bit

The PRG Response PASID Required bit in the PRI Capability is read-only.
Read it once when we enumerate the device and cache the value so we don't
need to read it again.

Based-on-patch-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/ats.c diff | blob | history
include/linux/pci.h diff | blob | history
Domain: System / Kernel;