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(parent: b6ee0bb) | patch
clk: renesas: r9a09g011: Add PFC clock and reset entries
authorPhil Edworthy <phil.edworthy@renesas.com>
Wed, 18 May 2022 13:52:08 +0000 (14:52 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 6 Jun 2022 09:13:30 +0000 (11:13 +0200)
commite55c4481e71de79d0ef566a238332bd346cef6de
tree2faa4be3751bfae367312fa79663d467de12a834tree | snapshot
parentb6ee0bbf388ab38384f92339aa9a1df15e716cfecommit | diff
clk: renesas: r9a09g011: Add PFC clock and reset entries

Add PFC clock/reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g011-cpg.c diff | blob | history
Domain: System / Kernel;