clk: pistachio: Fix override of clk-pll settings from boot loader
authorZdenko Pulitika <zdenko.pulitika@imgtec.com>
Wed, 26 Aug 2015 16:11:38 +0000 (17:11 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 26 Aug 2015 18:34:34 +0000 (11:34 -0700)
commite53f21c761d141bbcbce06e9ddab3b4e0a828f2c
treead980729395d4243da68dba63480b13c4064e569
parent093affb009a3d87848e51217cd1a06ce1135633f
clk: pistachio: Fix override of clk-pll settings from boot loader

PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: Andrew Bresitcker <abrestic@chromium.org>
Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/pistachio/clk-pll.c