Add barrier at start of each CB to order wrt previous CBs

Add barrier at start of each CB to order wrt previous CBs

Currently, there is only the implicit ordering guarantee for the top of
pipe between batches of commands. This isn't adequate for implementations
that allow overlapping work from different CBs. Insert an explicit
fairly-full barrier at the beginning of each CB to make this safe.

(Suggested by ARM to Google to deal with some long-standing weird
behavior)

Change-Id: I254db5f1461d5ff7c0af73de9219f59c8154df7c
Affects: dEQP-VK.memory.pipeline_barrier.*
Components: Vulkan
Google bug: b/113601409
VK-GL-CTS Issue: 1468