[MIPS GlobalISel] Select MSA vector generic and builtin add
authorPetar Avramovic <Petar.Avramovic@rt-rk.com>
Tue, 22 Oct 2019 13:51:57 +0000 (13:51 +0000)
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>
Tue, 22 Oct 2019 13:51:57 +0000 (13:51 +0000)
commite4af9de36ca60483040af381edd10e716e7b077d
treed3c47728f7423caaa58dca91f87789eff8f58744
parente5dd30f77e10b3fa3395312045c06e5e15f9620e
[MIPS GlobalISel] Select MSA vector generic and builtin add

Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_addv_<format> will be transformed into G_ADD
in legalizeIntrinsic and selected in the same way.
__builtin_msa_addvi_<format> will be directly selected into
ADDVI_<format> in legalizeIntrinsic. MIR tests for it have
unnecessary additional copies. Capture current state of tests
with run-pass=legalizer with a test in test/CodeGen/MIR/Mips.

Differential Revision: https://reviews.llvm.org/D68984

llvm-svn: 375501
llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll [new file with mode: 0644]
llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir [new file with mode: 0644]