spi: bcm63xx-hsspi: Fix multi-bit mode setting
authorWilliam Zhang <william.zhang@broadcom.com>
Thu, 9 Feb 2023 20:02:41 +0000 (12:02 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 10 Mar 2023 08:33:22 +0000 (09:33 +0100)
commite4aac4fb1dfeefa742c8151dcb274e09b1cbdf81
tree7bc1c37aad33166545f2bbad22b60198e1a25b19
parent3e2e193d5d8a756dd862a57dcb8533bc09b5d3cb
spi: bcm63xx-hsspi: Fix multi-bit mode setting

[ Upstream commit 811ff802aaf878ebbbaeac0307a0164fa21e7d40 ]

Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.

This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.

Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/spi/spi-bcm63xx-hsspi.c