[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.
authorHsiangkai Wang <hsiangkai@gmail.com>
Thu, 18 Jul 2019 14:47:34 +0000 (14:47 +0000)
committerHsiangkai Wang <hsiangkai@gmail.com>
Thu, 18 Jul 2019 14:47:34 +0000 (14:47 +0000)
commite43ce1a958aa0c2da41961f77a4dbd7ff97487e0
treeb14e6d28e1643600d2b14cbeb6f939f68a35c787
parent48104ef7c9c653bbb732b66d7254957389fea337
[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

It is necessary to generate fixups in .debug_frame or .eh_frame as
relaxation is enabled due to the address delta may be changed after
relaxation.

There is an opcode with 6-bits data in debug frame encoding. So, we
also need 6-bits fixup types.

Differential Revision: https://reviews.llvm.org/D58335

llvm-svn: 366442
18 files changed:
llvm/include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h
llvm/include/llvm/DebugInfo/DWARF/DWARFObject.h
llvm/include/llvm/MC/MCDwarf.h
llvm/include/llvm/MC/MCFixup.h
llvm/include/llvm/MC/MCFragment.h
llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
llvm/lib/MC/MCAsmBackend.cpp
llvm/lib/MC/MCAssembler.cpp
llvm/lib/MC/MCDwarf.cpp
llvm/lib/Object/RelocationResolver.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/test/CodeGen/RISCV/fixups-relax-diff.ll
llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
llvm/test/DebugInfo/RISCV/relax-debug-frame.ll [new file with mode: 0644]
llvm/test/MC/RISCV/fde-reloc.s
llvm/tools/dsymutil/DwarfLinker.cpp