Fix typo in vec_setv8hi_0.

Fix typo in vec_setv8hi_0.

pinsrw is available for both reg and mem operand under sse2.
pextrw requires sse4.1 for mem operands.

The patch change attr "isa" for pinsrw mem alternative from sse4_noavx
to noavx, will enable below optimization.

-        movzwl  (%rdi), %eax
         pxor    %xmm1, %xmm1
-        pinsrw  $0, %eax, %xmm1
+        pinsrw  $0, (%rdi), %xmm1
         movdqa  %xmm1, %xmm0

gcc/ChangeLog:

	PR target/105066
	* config/i386/sse.md (vec_set<mode>_0): Change attr "isa" of
	alternative 4 from sse4_noavx to noavx.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr105066.c: New test.