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clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
authorFinley Xiao <finley.xiao@rock-chips.com>
Tue, 17 Sep 2019 08:19:00 +0000 (10:19 +0200)
committerHeiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tue, 5 Nov 2019 19:53:30 +0000 (20:53 +0100)
commite40781098f56dab52e92b7651d87b38805536d28
treeb73483ceda7fad8ef883368561207beebedcb127tree | snapshot
parent762539d6999caa1d9a916a4ce72004977b2433cfcommit | diff
clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc

Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50%  duty
cycle, divfree50 can generate clock of 50% duty cycle even in odd
value divisor.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917081903.25139-2-heiko@sntech.de
drivers/clk/rockchip/clk-px30.c diff | blob | history
Domain: System / Kernel;